1. Field of the Invention
The invention relates to integrated circuits (ICs). More particularly, the invention relates to programmable input and output blocks for ICs.
2. Description of the Background Art
Programmable logic devices (PLDs) are a well known type of digital IC that may be programmed by a user (e.g., a circuit designer) to perform specified logic functions. PLDs are becoming ever more popular, largely because they are less expensive and require less time to implement than semi-custom and custom integrated circuits.
One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBS) that are programmably interconnected to each other and to programmable input/output blocks (IOBs). This collection of configurable elements may be customized by loading configuration data into internal configuration memory cells that define how the CLBs, interconnections, and IOBs are configured. The configuration data may be read from memory (e.g., an external PROM) or written into the FPGA from an external device. The collective states of the individual memory cells then determine the function of the FPGA.
IOBs provide the interface between external input/output (I/O) pads and the internal logic. Each IOB is typically associated with one I/O pad and can be configured for input, output, or bi-directional signals. FIG. 1 depicts a conventional IOB 100 similar to those of the XC4000EX.TM. family of devices available from Xilinx, Inc.
When configured as an input block, IOB 100 conveys digital input signals into the FPGA from I/O pad 115 through input buffer 116. These signals may be routed to the interior of the FPGA either directly, via line 118, or through register 120, as described in more detail below. IOB 100 also includes output circuitry 110 to convey signals from the FPGA to I/O pad 115 when IOB 100 is configured as an output block. A more complete discussion of output circuitry 110 and other circuits in IOB 100 can be found in pages 4-24 through 4-29 of "The Programmable Logic Data Book" (September, 1996) available from Xilinx, Inc., 2100 Logic Dr., San Jose, Calif., which pages are incorporated herein by reference. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.)
Data input through register 120 can be selectively delayed. The circuit of FIG. 1 has a two-tap delay circuit 130, offering choices of full delay (line 141), partial delay (line 142), or no delay (line 143). The amount of delay is user-specified by programming memory cells (not shown) to control the select inputs (also not shown) of a multiplexer 140. With the delay enabled, the setup and hold times of the input flip-flop are thereby modified so that normal clock routing does not result in a positive hold-time requirement, which could lead to unreliable system operation. An additional input path traverses a latch 135 gated by output clock OCLK that delays the input signal on line 118 until a signal is received from output clock OCLK. This programmable delay circuit is described in detail in Xilinx Application Note XAPP056, entitled "System Design with New XC4000X I/O Features, v. 1.2", published November 1997 and available from Xilinx, Inc., which is incorporated herein by reference.
IOBs are often used as input ports for serial data communications. Various modulation schemes have been devised to encode data into a serial format, allowing that data to be conveyed over a single electrical or optical conductor. Such schemes are conventionally self-clocking, which is to say that the clock used to interpret the input signal is derived from the input signal itself. Unfortunately, many random and systematic perturbations typically corrupt the signal. These perturbations can cause the timing relationship between the derived clock and the data signal to vary, causing noise conditions commonly referred to as "drift" and "jitter." These conditions differ in that drift occurs over a time period that is long relative to the period of the derived clock, whereas jitter occurs over a time period that is short relative to the period of the derived clock. For a more detailed discussion of jitter, including conventional methods for measuring jitter, see U.S. Pat. No. 5,481,563, entitled "Jitter Measurement Using a Statistically Locked Loop," which is incorporated herein by reference.